Redstone Logics LLC v. Qualcomm Inc. — Entry #62: Opposed MOTION to Stay Case Pending the Ex Parte Reexamination by Qualcomm Inc., Qualcomm Technologies, Inc
Case: Redstone Logics LLC v. Qualcomm Inc. txwd · 7:24-cv-00231
filed September 20, 2024
What this document is
Docket entry #62 · filed June 04, 2026
Opposed MOTION to Stay Case Pending the Ex Parte Reexamination by Qualcomm Inc., Qualcomm Technologies, Inc.. (Attachments: (1) Proposed Order, (2) Declaration of E. Green, (3) Exhibit 1, (4) Exhibit 2, (5) Exhibit 3, (6) Exhibit 4, (7) Exhibit 5, (8) Exhibit 6)(Leventhal, Daniel)
Who is involved
- Qualcomm Inc.
- Qualcomm Technologies, Inc.
- Redstone Logics LLC
Why we have it
We follow this case because it names a company we track, although that company is not a party:
- Marathon Digital: its former name “MARA Holdings, Inc.” appears in a filing in this case.
…... 1 Malikie Innovations LTD. et al v. Mara Holdings INC., No. 7:25-cv-00222-DC-DTG (W.D. Tex. June…
A free copy from the RECAP archive of federal court filings (mirrored at the Internet Archive), retrieved November 02, 2026. Federal court filings are public records.
Document text
167 page(s), 89,745 characters, converted from the PDF's text layer · plain text.
Full text
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EXHIBIT 2
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U.S. Patent No. 8,549,339 (“’339 Patent”)
Accused Products: Qualcomm’s products comprising one or more SoC each comprising two or more sets of processors
implementing or based on the DynamIQ Shared Unit architecture or big.LITTLE architecture, including without limitation: SM4250-
AA (Snapdragon 460), SM4350 (Snapdragon 480), SM4350-AC (Snapdragon 480+), SM4375 (Snapdragon 4 Gen 1), SM4450
(Snapdragon 4 Gen 2, Snapdragon 4 Gen 2 Accelerated Edition), SM4635 (Snapdragon 4s Gen 2), DM630 (Snapdragon 630), SDM632
(Snapdragon 632), SDM636 (Snapdragon 636), MSM8956 (Snapdragon 650), MSM8976 (Snapdragon 652), MSM8976 Pro
(Snapdragon 653), SDM660/SDA660 (Snapdragon 660), SM6115 (Snapdragon 662), SM6125 (Snapdragon 665), SDM670
(Snapdragon 670), SM6150 (Snapdragon 675), SM6150-AC (Snapdragon 678), SM6225 (Snapdragon 680), SM6225-AD (Snapdragon
685), SM6350 (Snapdragon 690), SM6375 (Snapdragon 695), SM6450 (Snapdragon 6 Gen 1), SM6115-AC (Snapdragon 6s Gen 1),
SM6475-AB (Snapdragon 6 Gen 3), SM6375-AC (Snapdragon 6s Gen 3), SDM710 (Snapdragon 710), SDM712 (Snapdragon 712),
SM7125 (Snapdragon 720G), SM7150-AA, (Snapdragon 730), SM7150-AB (Snapdragon 730G), SM7150-AC (Snapdragon 732G),
SM7225 (Snapdragon 750G), SM7325 (Snapdragon 778G), SM7325-AE (Snapdragon 778G+), SM7350-AB (Snapdragon 780G),
SM7325-AF (Snapdragon 782G), SM7435-AB (Snapdragon 7s Gen 2), SM7550-AB (Snapdragon 7 Gen 3), SM7675-AB (Snapdragon
7+ Gen 3), SM7635 (Snapdragon 7s Gen 3), MSM8992 (Snapdragon 808), MSM8994 (Snapdragon 810), MSM8994v2 (Snapdragon
810), MSM8994v2.1 (Snapdragon 810), MSM8996Lite (Snapdragon 820), MSM8996 (Snapdragon 820), MSM8996Pro-AB
(Snapdragon 821), MSM8996Pro-AC (Snapdragon 821), MSM8998 (Snapdragon 835), SDM845 (Snapdragon 845), SM8150
(Snapdragon 855), SM8150-AC (Snapdragon 855+), SM8150-AC (Snapdragon 860), SM8150P (Snapdragon 855+), SM8250
(Snapdragon 865), SM8250-AB (Snapdragon 865+), SM8250-AC (Snapdragon 870), SM8350 (Snapdragon 888), SM8350-AC
(Snapdragon 888+), SM8450 (Snapdragon 8 Gen 1), SM8475 (Snapdragon 8+ Gen 1), SM8425-100-AC (Snapdragon 8+ Gen 1 4G),
SM8550-AB (Snapdragon 8 Gen 2), SM8550-AC (Snapdragon 8 Gen 2 for Galaxy), SM8650-AB (Snapdragon 8 Gen 3), SM8650-AC
(Snapdragon 8 Gen 3 for Galaxy), SM8635 (Snapdragon 8s Gen 3), MSM8998 (Snapdragon 835 Mobile PC Platform), SDM850
(Snapdragon 850 Mobile Compute Platform), SC7180 (Snapdragon 7c), SC7180P (Snapdragon 7c Gen 2), SC7280 (Snapdragon 7c+
Gen 3), SC8180 (Snapdragon 8c), SC8180X (Snapdragon 8cx), SC8180XP (Snapdragon 8cx Gen 2), SC8280 (Snapdragon 8cx Gen 3),
MSM8996AU (Snapdragon 820A), SA6155P, SA8155P (Snapdragon 855A), SA8195P, SA8255P, SA8295P, APQ8094 (Snapdragon
810E), APQ8096 (Snapdragon 820E), QCS603, QCS605, XR1, XR2, XR2+ Gen 1, XR2 Gen 2, XR2+ Gen 2, G3x Gen 1, G3x Gen 2,
SQ1, SQ2, and SQ3.
Each Accused Product infringes the claims in substantially the same way, and the evidence shown in this chart is similarly
applicable to each Accused Product. For example, each Accused Product includes a DynamIQ Shared Unit or big.LITTLE architecture
and, on information and belief, implements substantially the same architectural features described in the reference documentation cited
in this chart. Thus, the descriptions and evidence below relating to the Snapdragon 8 Gen 2 Octa-Core and Snapdragon 835 Mobile
Platform representative products are similarly applicable to the remaining Accused Products listed above (for DynamIQ and big.LITTLE
architectures respectively). Each claim limitation is literally infringed by each Accused Product. However, to the extent any claim
1
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limitation is not met literally, it is nonetheless met under the doctrine of equivalents because the differences between the claim limitation
and each Accused Product would be insubstantial, and each Accused Product performs substantially the same function, in substantially
the same way, to achieve the same result as the claimed invention. Notably, Qualcomm has not yet articulated which, if any, particular
claim limitations it believes are not met by the Accused Products
Claim 1
Claim 1 Accused Products
[1pre] 1. A multi-core To the extent the preamble is limiting, each Accused Product comprises a multi-core processor.
processor, comprising:
For example, Snapdragon 8 Gen 2 Octa-Core processor, designated QCS8550 with die code name
Kailua, see Defendants’ Objections and Responses to Redstone Logics LLC’s First Set of
Interrogatories Nos. 1-15 (“ROG Responses”) at 15, contains eight cores implementing the ARM
DynamIQ Shared Unit-110 architecture. In a further example, the Snapdragon 835 Mobile
Platform contains eight cores implementing the ARM big.LITTLE architecture.
See, e.g.:
2
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Claim 1 Accused Products
https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems_on_chips#Snapdragon_8_
Gen_2_(2023)
3
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Claim 1 Accused Products
https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems_on_chips#Snapdragon_80
0_series_(2013%E2%80%932021)
4
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Claim 1 Accused Products
https://www.arm.com/technologies/dynamiq
5
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Claim 1 Accused Products
Arm Cortex-A510 Core Technical Reference Manual at p. 23
https://www.anandtech.com/show/11201/qualcomm-snapdragon-835-performance-preview/6
6
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Claim 1 Accused Products
“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
7
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Claim 1 Accused Products
“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
8
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Claim 1 Accused Products
[1a] a first set of processor Each Accused Product comprises a first set of processor cores of the multi-core processor,
cores of the multi-core wherein each processor core from the first set of processor cores is configured to dynamically
processor, wherein each receive a first supply voltage and a first output clock signal of a first phase lock loop (PLL) having
processor core from the first a first clock signal as input.
set of processor cores is
configured to dynamically For example, the Snapdragon 8 Gen 2 Octa-Core includes a first set of high efficiency processor
receive a first supply voltage cores (two or more ARM Cortex-A510 cores). The processor cores in the first set receive a
and a first output clock signal dynamic supply voltage and a first output clock signal of a first PLL having a first clock signal as
of a first phase lock loop input.
(PLL) having a first clock For another example, the Snapdragon 835 Mobile Platform includes a first set of high efficiency
signal as input; processor cores (two or more A53 cores). The processor core(s) in the first set receive a dynamic
supply voltage and a first output clock signal of a first PLL having a first clock signal as input.
ARM documentation for the big.LITTLE and DynamIQ architectures used in the Accused
Products directly shows that each core cluster receives its own clock domain. At the time the
Accused Products were designed, it was typical to produce this clock using a PLL that has a
corresponding clock input. Furthermore, ARM documentation for an earlier, related device (the
Cortex-A15_A7 MPCore test chip, which also has independent clock domains for different CPU
clusters) shows each CPU cluster receiving an output clock signal from a PLL having a
corresponding clock signal as input (e.g. from an oscillator).
See, e.g.:
9
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Claim 1 Accused Products
https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems_on_chips#Snapdragon_8_
Gen_2_(2023)
10
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Claim 1 Accused Products
https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems_on_chips#Snapdragon_80
0_series_(2013%E2%80%932021)
11
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Claim 1 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual, available at
https://documentation-service.arm.com/static/62bb28beb334256d9ea8cc32, at p. 19
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 22
12
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Claim 1 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 23
13
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Claim 1 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 24
14
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Claim 1 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 24
Arm® DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 25
15
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Claim 1 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 46
Arm Cortex-A510 Core Technical Reference Manual at p. 39
16
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Claim 1 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 46
https://developer.arm.com/documentation/101381/0400/Clocks-and-resets/Clocks-
17
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Claim 1 Accused Products
Arm® Total Compute 2021 Reference Design Software Developer Guide at p. 40
Id.
18
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Claim 1 Accused Products
Id. at p. 41
Id. at 47-48
19
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Claim 1 Accused Products
Id. at p. 48
Id. at p. 65
20
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Claim 1 Accused Products
https://www.anandtech.com/show/11201/qualcomm-snapdragon-835-performance-preview/6
“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
21
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Claim 1 Accused Products
“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
22
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Claim 1 Accused Products
“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
23
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Claim 1 Accused Products
ARM® CoreTile Express A15×2 A7×3 Technical Reference Manual, available at
https://developer.arm.com/documentation/ddi0503/i/
24
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Claim 1 Accused Products
Qualcomm’s documentation demonstrates that the accused devices are configured to contain a
first and second set of processor cores according to the above referenced architectures. For
example, both the Snapdragon 8 Gen 2 Octa-Core, die code Kailua, and Snapdragon 835 Mobile
Platform, MSM8998, are configured with a first set of “Gold” cores and a second set of “Silver”
cores, each set having its own PLL Gold or PLL Silver with its own input and output clock signal,
and each having a separate power domain and power rails, both the power and output clock signal
being variable and the clusters being configured to receive the same:
25
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Claim 1 Accused Products
26
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Claim 1 Accused Products
27
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Claim 1 Accused Products
QCREDSTONE_0098870 at -74, -83, -84, -96.
28
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Claim 1 Accused Products
QCREDSTONE_0123173 at -73, -77.
QCREDSTONE_0039762 at -71
29
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Claim 1 Accused Products
QCREDSTONE_0082868 at -878.
30
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Claim 1 Accused Products
QCREDSTONE_0091042 at -44.
31
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Claim 1 Accused Products
QCREDSTONE_0098768 at -70.
This arrangement of Gold+, Gold, and/or Silver cores arranged into clusters according to the
above referenced architectures is repeated throughout the accused products1:
1
Qualcomm has failed to produce similar diagrams for all accused products/dies or even identified all relevant dies, however the cited documentation
demonstrates a common infringing design across all accused products.
32
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Claim 1 Accused Products
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Claim 1 Accused Products
35
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Claim 1 Accused Products
QCREDSTONE_0098556 at -558 to -562.
36
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Claim 1 Accused Products
QCREDSTONE_0090058 at -71.
37
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Claim 1 Accused Products
38
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Claim 1 Accused Products
39
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Claim 1 Accused Products
QCREDSTONE_0091177 at -86-87, -248.
40
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Claim 1 Accused Products
41
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Claim 1 Accused Products
QCREDSTONE_0123173 at -173 to -177, -183, -316. See also QCREDSTONE_0108055,
QCREDSTONE_010943, QCREDSTONE_0110523, QCREDSTONE_0112461,
QCREDSTONE_0113841, QCREDSTONE_0114427, QCREDSTONE_0115813,
QCREDSTONE_0116536, QCREDSTONE_0117594; QCREDSTONE_0120263,
QCREDSTONE_0124233, QCREDSTONE_0125186, QCREDSTONE_0131099.
42
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Claim 1 Accused Products
QCREDSTONE_0099078 at -82 to -83.
43
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Claim 1 Accused Products
QCREDSTONE_0090953 at -84.
44
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Claim 1 Accused Products
45
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Claim 1 Accused Products
QCREDSTONE_0092294 at -96, -97.
46
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Claim 1 Accused Products
QCREDSTONE_0013455 At -64, -65.
47
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Claim 1 Accused Products
QCREDSTONE_0096091 at -104.
[1b] a second set of processor Each Accused Product comprises a second set of processor cores of the multi-core processor,
cores of the multi-core wherein each processor core from the second set of processor cores is configured to dynamically
processor, wherein each receive a second supply voltage and a second output clock signal of a second PLL having a second
processor core from the second clock signal as input, wherein the first supply voltage is independent from the second supply
set of processor cores is voltage, and the first clock signal is independent from the second clock signal.
configured to dynamically
receive a second supply For example, in addition to the first set of processor cores, the Snapdragon 8 Gen 2 Octa-Core has
a second set of high-performance processor cores (two or more ARM Cortex-A710 cores). For
48
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Claim 1 Accused Products
voltage and a second output another example, in addition to the first set of processor cores, the Snapdragon 8 Gen 2 Octa-Core
clock signal of a second PLL has a second set of high-performance processor cores (two or more ARM Cortex-A715 cores).
having a second clock signal The processor cores in the second set receive a second, independent dynamic supply voltage and a
as input, wherein the first second clock signal of a second PLL receiving an independent second clock signal.
supply voltage is independent
from the second supply For a further example, in addition to the first set of processor cores, the Snapdragon 835 Mobile
voltage, and the first clock Platform has a second set of high-performance processor cores (two or more A73 cores). The
signal is independent from the processor cores in the second set receive a second, independent dynamic supply voltage and a
second clock signal; and second clock signal of a second PLL receiving an independent second clock signal.
ARM documentation for the big.LITTLE and DynamIQ architectures used in the Accused
Products directly shows that each core cluster receives its own clock domain. At the time the
Accused Products were designed, it was typical to produce this clock using a PLL that has a
corresponding clock input. Furthermore, ARM documentation for an earlier, related device (the
Cortex-A15_A7 MPCore test chip, which also has independent clock domains for different CPU
clusters) shows each CPU cluster receiving an output clock signal from a PLL having a
corresponding clock signal as input (e.g. from an oscillator).
See, e.g.:
49
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Claim 1 Accused Products
https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems_on_chips#Snapdragon_8_
Gen_2_(2023)
50
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Claim 1 Accused Products
https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems_on_chips#Snapdragon_80
0_series_(2013%E2%80%932021)
51
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Claim 1 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual, available at
https://documentation-service.arm.com/static/62bb28beb334256d9ea8cc32, at p. 19
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 22
52
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Claim 1 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 23
53
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Claim 1 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 24
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Claim 1 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 24
Arm® DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 25
55
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Claim 1 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 46
56
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Claim 1 Accused Products
Id. at p. 78
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Claim 1 Accused Products
Arm Cortex-A510 Core Technical Reference Manual at p. 39
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 46
https://developer.arm.com/documentation/101381/0400/Clocks-and-resets/Clocks-
58
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Arm® Total Compute 2021 Reference Design Software Developer Guide at p. 40
Id.
59
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Claim 1 Accused Products
Id. at p. 41
Id. at 47-48
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Claim 1 Accused Products
Id. at p. 48
Id. at p. 65
61
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https://www.anandtech.com/show/11201/qualcomm-snapdragon-835-performance-preview/6
“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
62
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“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
63
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“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
64
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ARM® CoreTile Express A15×2 A7×3 Technical Reference Manual, available at
https://developer.arm.com/documentation/ddi0503/i/
65
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Qualcomm’s documentation demonstrates that the accused devices are configured to contain a
first and second set of processor cores according to the above referenced architectures. For
example, both the Snapdragon 8 Gen 2 Octa-Core, die code Kailua, and Snapdragon 835 Mobile
Platform, MSM8998, are configured with a first set of “Gold” cores and a second set of “Silver”
cores, each set having its own PLL Gold or PLL Silver with its own input and output clock signal,
and each having a separate power domain and power rails, both the power and output clock signal
being variable and the clusters being configured to receive the same:
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67
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68
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QCREDSTONE_0098870 at -74, -83, -84, -96.
69
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QCREDSTONE_0123173 at -73, -77.
QCREDSTONE_0039762 at -71
70
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QCREDSTONE_0082868 at -878.
71
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QCREDSTONE_0091042 at -44.
72
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QCREDSTONE_0098768 at -70.
Additionally, Qualcomm documentation shows that each cluster of cores, e.g. gold and silver, is in
a different power domain and clock domain, configured to provide independent voltages and clock
signals to each cluster:
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74
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75
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QCREDSTONE_0098870 at -74, -83, -84, -96.
76
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QCREDSTONE_0123173 at -73, -77.
QCREDSTONE_0039762 at -71
77
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This arrangement of Gold+, Gold, and/or Silver cores arranged into clusters according to the
above referenced architectures is repeated throughout the accused products:
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79
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80
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QCREDSTONE_0098556 at -558 to -562.
81
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QCREDSTONE_0090058 at -71.
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83
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84
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QCREDSTONE_0091177 at -86-87, -248.
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86
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QCREDSTONE_0123173 at -173 to -177, -183, -316. See also QCREDSTONE_0108055,
QCREDSTONE_010943, QCREDSTONE_0110523, QCREDSTONE_0112461,
QCREDSTONE_0113841, QCREDSTONE_0114427, QCREDSTONE_0115813,
QCREDSTONE_0116536, QCREDSTONE_0117594; QCREDSTONE_0120263,
QCREDSTONE_0124233, QCREDSTONE_0125186, QCREDSTONE_0131099.
87
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QCREDSTONE_0099078 at -82 to -83.
88
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QCREDSTONE_0090953 at -84.
89
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90
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QCREDSTONE_0092294 at -96, -97.
91
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QCREDSTONE_0013455 At -64, -65.
92
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QCREDSTONE_0096091 at -104.
[1c] an interface block coupled Each Accused Product comprises an interface block coupled to the first set of processor cores and
to the first set of processor also coupled to the second set of processor cores, wherein the interface block is configured to
cores and also coupled to the facilitate communication between the first set of processor cores and the second set of processor
second set of processor cores, cores.
wherein the interface block is
configured to facilitate For example, the Snapdragon 8 Gen 2 Octa-Core includes a DynamIQ Shared Unit (DSU),
communication between the including a Snoop Control Unit (SCU), that is coupled to each core or to each set of processor
cores and is configured to communicate between the sets of processor cores, including by
93
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first set of processor cores and buffering and resynchronizing signals across clock domains and by maintaining coherency
the second set of processor between caches in the cores or complexes and/or with the L3 shared memory implemented by the
cores. DSU.
For another example, the Snapdragon 835 Mobile Platform includes a cache coherent
interconnect, such as a CCI-400 or CCI-550, that is coupled to each core or to each set of
processor cores and is configured to communicate between the sets of processor cores, for
example by maintaining coherency between caches in the cores or complexes.
As shown in the relevant documentation, described above and reiterated here for the avoidance of
all possible doubt, the Accused Products implement either the big.LITTLE or DynamIQ
architecture, which are the heterogeneous processing architectures for the ARM Cortex-A53/A72
and ARM Cortex-A510/A710/A715 respectively.
The big.LITTLE architecture is also the heterogenous processing architecture for the ARM
Cortex-A7 and Cortex-A15 processors. For example, ARM documentation for the big.LITTLE
architecture expressly includes all four of these processors in its stated scope. ARM’s public
documentation of the big.LITTLE architecture describes the infringing cache coherent
interconnect in general, and also in the context of a ”typical big.LITTLE system” featuring
Cortex-A7 and Cortex-A15 processors. There is a reasonable inference that ARM’s document also
applies to the Accused Products with big.LITTLE architectures including Cortex-A53 and Cortex-
A72 cores.
And the ARM documentation for the ARM Cortex-A510 processor core expressly states that it
includes and supports the DynamIQ Shared Unit (DSU), creating a reasonable inference that
ARM’s DSU documentation also applies to the Accused Products with DynamIQ architectures
including Cortex-A510, Cortex-A710, and/or Cortex-A715 cores.
Qualcomm documentation likewise confirms the use of DSU and cache coherency interconnects,
such as with a “Gladiator NOC,” in the manner described above to facilitate communication
between the clusters.
See, e.g.:
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Arm Cortex-A510 Core Technical Reference Manual at p. 39
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 34
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 18
95
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Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 35
96
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Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 17
“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
97
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“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
98
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“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/
99
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ARM White Paper “big.LITTLE Technology: The Future of Mobile Making very high
performance available in a mobile envelope without sacrificing energy efficiency,” available at
https://armkeil.blob.core.windows.net/developer/Files/pdf/white-paper/big-little-technology-the-
future-of-mobile.pdf
100
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ARM White Paper “big.LITTLE Technology: The Future of Mobile Making very high
performance available in a mobile envelope without sacrificing energy efficiency,” available at
https://armkeil.blob.core.windows.net/developer/Files/pdf/white-paper/big-little-technology-the-
future-of-mobile.pdf
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ARM White Paper “big.LITTLE Technology: The Future of Mobile Making very high
performance available in a mobile envelope without sacrificing energy efficiency,” available at
https://armkeil.blob.core.windows.net/developer/Files/pdf/white-paper/big-little-technology-the-
future-of-mobile.pdf
102
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ARM White Paper “big.LITTLE Technology: The Future of Mobile Making very high
performance available in a mobile envelope without sacrificing energy efficiency,” available at
https://armkeil.blob.core.windows.net/developer/Files/pdf/white-paper/big-little-technology-the-
future-of-mobile.pdf
QCREDSTONE_0082759 at -72.
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QCREDSTONE_0036560 at -71
104
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QCREDSTONE_0082868 at-78.
105
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QCREDSTONE_0087481 at -93.
106
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QCREDSTONE_0087836 at -39.
107
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QCREDSTONE _0088972 at -91.
108
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QCREDSTONE_0089100 at -04.
109
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QCREDSTONE_0098768 at -70.
110
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QCREDSTONE_0090274 at -91, -92.
111
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QCREDSTONE_0091858 at -66.
112
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QCREDSTONE_0098363.
Claim 5
Claim 5 Accused Products
5. The multi-core processor of Each Accused Product comprises a multi-core processor of claim 1, wherein the first set of
claim 1, wherein the first set of processor cores and the second set of processor cores are configured to receive one or more
processor cores and the second control signals from one or more control blocks located in a periphery of the multi-core processor.
set of processor cores are
configured to receive one or For example, according to ARM’s documents and reference design, the multi-core processor
more control signals from one should contain a system control processor (SCP) to control voltage, power, and clocks, and power
policy units (PPUs) to manage power states on each voltage domain. On information and belief,
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or more control blocks located each DynamIQ Accused Product contains an SCP and one or more PPUs as described.
in a periphery of the multi-core Identification of the physical location of the control blocks is proprietary information of
processor. Qualcomm that is the proper subject of fact discovery and to date no production detailing the
physical location of any blocks has been made.
For another example, according to ARM’s documents and reference design, a big.LITTLE multi-
core processor should contain a power controller and other controllers for supplying control
signals as claimed. Identification of the physical location of the control blocks is proprietary
information of Qualcomm that is the proper subject of fact discovery and to date no production
detailing the physical location of any such blocks has been made.
See, e.g.:
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Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 78
115
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Arm® Total Compute 2021 Reference Design Software Developer Guide at 47-48
116
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Id. at p. 65
117
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“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/, at 15 (2-3)
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Id.
Id.
Qualcomm’s documentation confirms the accused products include the same or similar SCP, PPU,
and Power Controller blocks.
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120
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121
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QCREDSTONE_0098870 at -74, -83, -84.
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QCREDSTONE_0098768 at -70.
123
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124
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125
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QCREDSTONE_0098556 at -558 to -562.
126
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127
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QCREDSTONE_0091177 at -86-87.
Claim 8
Claim 8 Accused Products
8. The multi-core processor of Each Accused Product comprises a multi-core processor of claim 1, wherein the first set of
claim 1, wherein the first set of processor cores are located in a first region of the multi-core processor, and the second set of
processor cores are located in a processor cores are located in a second region of the multi-core processor.
first region of the multi-core
processor, and the second set For example, on information and belief each core is located a region of the multi-core processor.
of processor cores are located Identification of the physical arrangement of the cores is proprietary information of Qualcomm
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in a second region of the that is the proper subject of fact discovery and to date no production detailing the physical
multi-core processor. location of any blocks has been made.
See, e.g.:
Arm® Total Compute 2021 Reference Design Software Developer Guide at 15
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https://www.androidauthority.com/snapdragon-8-gen-2-explained-3231826/
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“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/, at 15 (2-3)
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Claim 8 Accused Products
On information and belief, Qualcomm physically groups components, including groups of
processor cores based on common voltages/power such groups of processor cores such as the first
and second processor cores are each physically grouped together as they use voltage APC0 and
APC1 respectively, see e.g. QCREDSTONE_0091177 at -87, -87, QCREDSTONE_0096091 at -
104:
132
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QCREDSTONE_0031600 at -21.
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Claim 9
Claim 9 Accused Products
9. The multi-core processor of Each Accused Product comprises a multi-core processor of claim 8, wherein the first region and
claim 8, wherein the first the second region are overlapping regions of the multi-core processor.
region and the second region
are overlapping regions of the For example, on information and belief there is either some overlap or no overlap of the first and
multi-core processor. second regions. Identification of the physical arrangement of the cores is proprietary information
of Qualcomm that is the proper subject of fact discovery and to date no production detailing the
physical location of any blocks has been made.
Claim 10
Claim 10 Accused Products
10. The multi-core processor Each Accused Product comprises a multi-core processor of claim 8, wherein the first region and
of claim 8, wherein the first the second region are non-overlapping regions of the multi-core processor.
region and the second region
are non-overlapping regions of For example, on information and belief there is either some overlap or no overlap of the first and
the multi-core processor. second regions. Identification of the physical arrangement of the cores is proprietary information
of Qualcomm that is the proper subject of fact discovery and to date no production detailing the
physical location of any blocks has been made.
On information and belief, Qualcomm physically groups components, including groups of
processor cores based on common voltages/power such groups of processor cores such as the first
and second processor cores are each physically grouped together as they are in power domain
APC0 and APC1 respectively, see e.g. QCREDSTONE_0091177 at -87, -87,
QCREDSTONE_0096091 at -104:
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QCREDSTONE_0031600 at -21.
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Claim 21
Claim 21 Accused Products
[21pre]. A multi-core To the extent the preamble is limiting, each Accused Product comprises a multi-core processor.
processor, comprising:
See analysis and evidence of claim 1 preamble above.
[21a] a first set of processor Each Accused Product comprises a first set of processor cores of the multi-core processor,
cores of the multi-core wherein each processor core from the first set of processor cores is configured to dynamically
processor, wherein each receive a first supply voltage from a power control block and a first output clock signal from a
processor core from the first first phase lock loop (PLL) having a first clock signal as input in a clock control block.
set of processor cores is
configured to dynamically See analysis and evidence of claim element [1a] above.
receive a first supply voltage Furthermore, each DynamIQ Accused Product includes a power control block and a clock control
from a power control block block. For example, according to ARM’s documents and reference design, the multi-core
and a first output clock signal processor should contain a system control processor (SCP) to control voltage, power, and clocks,
from a first phase lock loop and power policy units (PPUs) to manage power states on each voltage domain. On information
(PLL) having a first clock and belief, the processor in each DynamIQ Accused Product contains an SCP and one or more
signal as input in a clock PPUs as described.
control block;
For another example, according to ARM’s documents and reference design, a big.LITTLE multi-
core processor should contain a power controller and other controllers for supplying the voltage
and clock signals as claimed.
See, e.g.:
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Claim 21 Accused Products
Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 78
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Claim 21 Accused Products
Arm® Total Compute 2021 Reference Design Software Developer Guide at 47-48
138
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Id. at p. 65
139
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“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/, at 15 (2-3)
140
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Id.
Id.
Qualcomm’s documentation confirms the accused products include the same or similar SCP, PPU,
and Power Controller blocks.
141
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142
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143
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QCREDSTONE_0098870 at -74, -83, -84.
144
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Claim 21 Accused Products
QCREDSTONE_0098768 at -70.
145
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146
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147
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Claim 21 Accused Products
QCREDSTONE_0098556 at -558 to -562.
148
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149
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Claim 21 Accused Products
QCREDSTONE_0091177 at -86-87.
[21b] a second set of processor Each Accused Product comprises a second set of processor cores of the multi-core processor,
cores of the multi-core wherein each processor core from the second set of processor cores is configured to dynamically
processor, wherein each receive a second supply voltage from the power control block and a second output clock signal
processor core from the second from a second PLL having a second clock signal as input in the clock control block, wherein the
set of processor cores is first supply voltage is independent from the second supply voltage, and the first clock signal is
configured to dynamically independent from the second clock signal
receive a second supply
voltage from the power control See analysis and evidence of claim element [1b] above.
block and a second output Furthermore, each DynamIQ Accused Product includes a power control block and a clock control
clock signal from a second block. For example, according to ARM’s documents and reference design, the multi-core
PLL having a second clock processor should contain a system control processor (SCP) to control voltage, power, and clocks,
150
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Claim 21 Accused Products
signal as input in the clock and power policy units (PPUs) to manage power states on each voltage domain. On information
control block, wherein the first and belief, each DynamIQ Accused Product contains an SCP and one or more PPUs as described.
supply voltage is independent
from the second supply For another example, according to ARM’s documents and reference design, a big.LITTLE multi-
voltage, and the first clock core processor should contain a power controller and other controllers for supplying the voltage
signal is independent from the and clock signals as claimed. On information and belief, each big.LITTLE Accused Product
second clock signal; and contains a power controller and other controllers as described.
See, e.g.:
151
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Arm DynamIQ™ Shared Unit-110 Technical Reference Manual at p. 78
152
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Arm® Total Compute 2021 Reference Design Software Developer Guide at 47-48
153
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Id. at p. 65
154
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“High-level Considerations for Power Management of a big.LITTLE™ System Application Note
424,” available at https://developer.arm.com/documentation/dai0424/a/, at 15 (2-3)
155
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Id.
Id.
Qualcomm’s documentation confirms the accused products include the same or similar SCP, PPU,
and Power Controller blocks.
156
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157
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158
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QCREDSTONE_0098870 at -74, -83, -84.
159
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QCREDSTONE_0098768 at -70.
160
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161
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162
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QCREDSTONE_0098556 at -558 to -562.
163
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164
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QCREDSTONE_0091177 at -86-87.
[21c] an interface block Each Accused Product comprises an interface block coupled to the first set of processor cores and
coupled to the first set of also coupled to the second set of processor cores, wherein the interface block is configured to
processor cores and also facilitate communication between the first set of processor cores and the second set of processor
coupled to the second set of cores.
processor cores, wherein the
interface block is configured to See analysis and evidence of claim element [1c] above.
facilitate communication
between the first set of
processor cores and the second
set of processor cores.
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166
