jain.com — data centers, connectivity and security, analyzed daily

Tag: Nvidia

  • 800VDC and the Megawatt Rack: How High-Voltage DC Reshapes Data Center Cooling

    800VDC and the Megawatt Rack: How High-Voltage DC Reshapes Data Center Cooling

    Data Center Dynamics has published an analysis of 800-volt direct current (800VDC) power distribution and its knock-on effects for data center cooling, examining the infrastructure evolution and operational impact of the architecture now being proposed for next-generation AI racks. The piece lands as the industry debates how facilities designed around alternating current (AC) and 54-volt in-rack distribution adapt to rack power densities approaching a megawatt.

    Executive Summary

    The subject is a plumbing-and-wiring story with strategic stakes: as AI accelerator racks climb toward megawatt-class power draws, the conventional approach — converting utility AC power through multiple stages down to low-voltage DC inside the rack — runs into hard physical limits on copper, conversion losses, and space. Moving distribution to 800VDC, an approach publicly championed by NVIDIA and partners across the power-electronics ecosystem for its next-generation rack designs, promises fewer conversion stages, dramatically thinner conductors, and higher end-to-end efficiency.

    The DCD analysis focuses on the less-discussed second-order effect: what this does to cooling. Every watt saved in power conversion is a watt of heat that never has to be removed, but the racks 800VDC enables are so dense that liquid cooling becomes a prerequisite rather than an option. Power architecture and thermal architecture, historically designed by separate teams against separate budgets, are converging into a single engineering problem — and operators, colocation providers, and equipment vendors will all feel the shift.

    Why a Power Story Is Really a Cooling Story

    In a data center, electricity and heat are two views of the same quantity: essentially all power delivered to IT equipment leaves as heat that the cooling plant must reject. Every stage of power conversion — utility voltage to distribution voltage, AC to DC, high DC to the roughly one volt a chip core actually uses — wastes a slice of energy as heat, often inside the white space where cooling is most expensive. Collapsing conversion stages with 800VDC distribution reduces that parasitic load. But the same architecture exists to feed racks far denser than air can handle: at hundreds of kilowatts per rack and beyond, direct-to-chip liquid cooling with cold plates, coolant distribution units (CDUs), and facility water loops stops being an exotic option and becomes the baseline design.

    That coupling changes how facilities get engineered. Busbar routing, cold-plate manifolds, leak detection, and serviceability now compete for the same rack volume. The DCD piece’s framing — implications, infrastructure evolution, operational impact — reflects a real shift in the industry conversation from “can we power it” to “can we power and cool it as one integrated system.”

    What Actually Changes Between 54 Volts and 800

    Today’s high-density AI racks typically distribute power internally at around 54 volts DC over copper busbars. Power scales with voltage times current, so at fixed voltage, a megawatt rack demands enormous current — and current is what sizes conductors, connectors, and their resistive losses. Raising distribution to 800VDC cuts the current for the same power by an order of magnitude, which is why the approach shrinks copper requirements and frees rack space for compute and cooling hardware. It also moves bulky AC-to-DC conversion equipment out of the rack into dedicated infrastructure, a further gift of space and a relocation of its heat.

    For the thermal engineer, the ripple effects are concrete: less conversion loss inside the rack, but far more total heat per rack; new hot components (DC converters, solid-state protection devices) in new places; and coolant loops that must be designed around high-voltage conductors with appropriate creepage, isolation, and leak-response assumptions. None of this is unsolvable — electric vehicles and utility-scale solar have normalized high-voltage DC engineering — but it is genuinely new practice for most data center operations teams.

    The Operational Bill: Skills, Safety, and Serviceability

    The quiet cost of the transition is human. Data center technicians are trained on AC systems and low-voltage DC; 800VDC introduces different arc-flash behavior, different lockout and protection practices, and different failure modes, now interleaved with pressurized liquid-cooling loops in the same enclosure. Procedures for a coolant leak near an energized 800V busbar have to be written, trained, and drilled before the first rack lands. Vendors will point to sealed, engineered systems; operators will reasonably ask who is qualified to service them and on what schedule.

    There is also a monitoring and commissioning dimension. When power and cooling are co-designed, so must be their telemetry: a CDU fault and a DC bus fault can each cascade into the other’s domain within seconds at megawatt densities. Operators evaluating 800VDC-era equipment should scrutinize integration of electrical and thermal controls as closely as the headline efficiency figures.

    Winners, Losers, and the Retrofit Question

    The clearest beneficiaries are power-electronics and liquid-cooling suppliers, which gain a generational replacement cycle, and hyperscale builders designing greenfield AI factories where the whole electrical-thermal stack can be specified at once. The harder position belongs to operators of existing facilities: buildings engineered around air cooling, AC distribution, and 10–30 kW racks cannot simply be re-declared 800VDC-ready. Some will retrofit power and cooling in tandem; others will find their most valuable asset is grid connection and land rather than the building itself.

    For colocation providers and enterprise buyers, the pragmatic takeaway is sequencing. 800VDC is a roadmap item tied to next-generation rack platforms, not a description of most 2026 deployments — but cooling and electrical decisions made today have 15-to-20-year design lives. Facilities being planned now should at minimum preserve optionality: structural allowances for liquid loops, space for DC plant, and staff development that anticipates high-voltage practice.

    Background

    Data center power delivery has evolved in steps: from AC distribution to the server, to rack-level busbars at 12 and then 54 volts DC, each change driven by rising density. The AI buildout broke the curve — accelerator racks jumped from tens of kilowatts to hundreds, with roadmaps pointing toward a megawatt per cabinet, forcing the industry to revisit both how power reaches silicon and how heat leaves it. In 2025, NVIDIA and a wide ecosystem of power and cooling partners publicly outlined 800VDC distribution for next-generation rack platforms, borrowing high-voltage DC practice from electric vehicles and utility-scale solar.

    Data Center Dynamics, the trade publication behind the source analysis, has tracked the parallel rise of liquid cooling from niche to necessity. The convergence of those two threads — high-voltage power and liquid thermal management as one co-designed system — is the backdrop for this piece and for facility design decisions now being made with multi-decade consequences.

    Source: 800VDC data center cooling: Implications, infrastructure evolution and operational impact — Data Center Dynamics analysis of how 800-volt DC power architecture reshapes data center cooling design and operations, published April 24, 2026.

  • Google Unveils New AI Chips for Training and Inference in Latest Challenge to Nvidia

    Google Unveils New AI Chips for Training and Inference in Latest Challenge to Nvidia

    Google has unveiled a new generation of custom chips designed to handle both AI training — the compute-intensive process of building large models — and inference, the day-to-day work of running them, according to CNBC coverage published April 21, 2026. The announcement is the latest move in Google’s decade-long effort to reduce its dependence on Nvidia, whose graphics processing units (GPUs) dominate the market for AI accelerators.

    Executive Summary

    The announcement, as reported, positions Google’s newest silicon as a dual-purpose platform: one chip family aimed at both building frontier AI models and serving them to users at scale. That framing matters. Training has historically drawn the headlines, but inference — every chatbot reply, every AI-generated search answer — is where the industry’s recurring costs now accumulate, and where cloud providers have the strongest incentive to control their own hardware economics.

    It is worth being direct about what is and is not substantiated here. The coverage available at publication is headline-level: it confirms that new chips exist and that they target both workloads, but it does not, in the material we reviewed, disclose performance figures, availability dates, pricing, or named customers. Our analysis therefore focuses on the well-documented market context this announcement lands in, rather than on claims the source does not support.

    What is beyond dispute is the strategic direction. Google has designed its own Tensor Processing Units (TPUs) since the mid-2010s, and each new generation tightens the competitive pressure on Nvidia — not by selling chips against it, but by giving one of the world’s largest AI operators, and its cloud customers, a credible alternative.

    The Custom-Silicon Race Enters a New Phase

    Every major cloud provider now designs its own AI accelerators. Google was earliest with its TPU line, Amazon Web Services followed with Trainium and Inferentia, and Microsoft has developed its Maia chips. The motivation is the same across all three: Nvidia’s GPUs are extraordinarily capable but also expensive, supply-constrained, and sold on Nvidia’s terms. For companies spending tens of billions of dollars a year on AI infrastructure, even a modest cost or efficiency advantage from in-house silicon compounds into enormous savings.

    A new TPU generation covering both training and inference signals that Google intends to compete across the full AI lifecycle, not just in niches. That is a meaningful escalation. Custom chips that only serve inference concede the most prestigious workloads — frontier model training — to Nvidia. A chip family credibly pitched at both erodes that concession.

    Why Pairing Training and Inference Matters

    Training a large model is a massive one-time (or periodic) expense; inference is a cost that scales with every user, every query, every day. As AI products move from demos to mass deployment, industry attention has shifted toward the price of serving models — often measured in cost per token, the basic unit of AI text processing. Hardware optimized for inference can trade raw flexibility for efficiency, lowering that recurring bill.

    Announcing one platform for both workloads also simplifies the operational picture inside data centers. Operators can, in principle, shift capacity between training and serving as demand fluctuates, rather than maintaining separate fleets. Whether Google’s new chips actually deliver that flexibility is exactly the kind of claim that requires benchmarks the coverage does not yet provide.

    The Economics of Not Selling Chips

    Google’s challenge to Nvidia is structurally unusual: Google has historically not sold TPUs as merchant silicon. Instead, it rents access to them through Google Cloud and uses them to run its own services. The competitive effect is indirect but real — every workload that runs on a TPU is a workload Nvidia doesn’t monetize, and every credible TPU generation strengthens Google’s negotiating position when it does buy Nvidia hardware, which it continues to do at scale.

    The harder question is software. Nvidia’s dominance rests as much on CUDA — its mature, widely adopted programming ecosystem — as on its chips. Developers, frameworks, and years of accumulated code default to Nvidia. Google’s counter has been to optimize its own software stack for TPUs, which works well inside Google and for cloud customers willing to adapt, but keeps the broader market’s center of gravity with Nvidia. A new chip alone does not change that; sustained software investment might.

    What It Means for the Infrastructure Layer

    For data center operators and the wider infrastructure industry, chip diversity is broadly good news. A market with multiple viable accelerators eases the supply bottlenecks that have delayed AI buildouts, and competition on efficiency directly shapes facility design — modern AI accelerators drive rack power densities that increasingly demand liquid cooling and substantial electrical upgrades.

    For enterprise AI buyers, the practical takeaway is optionality. Cloud customers evaluating where to train or serve models now have a genuine multi-vendor landscape to price against, even if switching costs remain significant. The winners in that dynamic are large-scale buyers; the risk sits with anyone betting that any single vendor’s roadmap — Nvidia’s included — will define the market indefinitely.

    Background

    Google was the first hyperscaler to design its own AI accelerator, deploying Tensor Processing Units internally in the mid-2010s and offering them to cloud customers later that decade. The program began as a way to run Google’s own AI services more efficiently and has since become a strategic pillar of Google Cloud’s pitch to AI developers. Nvidia, meanwhile, transformed from a graphics-chip company into the dominant supplier of AI compute, with its GPUs powering the vast majority of large-model training worldwide and its market value soaring on AI demand.

    That dominance made Nvidia’s largest customers — Google, Amazon, Microsoft, and Meta among them — also its most motivated potential competitors. Each now invests heavily in custom silicon, not necessarily to sell chips, but to control the cost and supply of the infrastructure their AI ambitions depend on. This announcement is the latest chapter in that structural tension.

    Source: Google unveils chips for AI training and inference in latest shot at Nvidia — CNBC report, April 21, 2026, on Google’s newest custom AI accelerators.