TL;DR · 30-second read

The Short Version

Two major chipmakers, GlobalFoundries and Taiwan Semiconductor Manufacturing Company, the world’s largest contract chipmaker, have struck a $2 billion deal to make a key chip part in the United States.

The part is a silicon “interposer”: a thin slab of silicon that sits under an artificial intelligence processor and wires it to its memory, like a shared floor both chips are mounted on. The packaging step built around it has been one of the main limits on how many artificial intelligence chips get shipped.

Making it in America could add supply outside Taiwan. But it covers one step, not the whole chip.

Yahoo Finance reported that GlobalFoundries and TSMC have reached a $2 billion deal for silicon interposers produced in the United States. Silicon interposers are the base layer in the advanced packages that join high-end AI processors to stacked high-bandwidth memory, which places the agreement inside the part of the GPU supply chain that has repeatedly constrained output.

The deal follows TSMC’s October 8 Form 6-K, its September 2026 revenue report, which showed consolidated revenue of roughly NT$511.86 billion for the month, up 54.6 percent from September 2025, and NT$3,898.73 billion for January through September, up 41.1 percent year over year.

Executive Summary

The headline facts are simple: a $2 billion agreement between the world’s largest contract chipmaker and a US-headquartered specialty foundry, covering a component that is made in the United States. The interposer is not a commodity part. It is a large piece of silicon, patterned in a wafer fab with fine wiring and vertical connections called through-silicon vias. AI accelerators mount their compute die and memory stacks on it side by side.

That matters because AI chip supply has been gated less by the ability to make processors than by the ability to package them with memory. Making interposers in the US adds a domestic source for one input to that packaging flow. However, an interposer is an intermediate part. Until the companies say where the rest of the package is assembled, the deal shows where part of the bottleneck can be relieved, not that it has been.

For GlobalFoundries, a $2 billion commitment tied to AI packaging is a significant new line for a foundry that stepped back from the leading-edge process race in 2018. For TSMC, whose September revenue alone was more than NT$500 billion, the deal is small in financial terms. Its importance is geographic and logistical.

Why the Interposer Sits on AI’s Critical Path

The most capable AI accelerators are not a single chip. They are assemblies. A large processor die sits next to several stacks of high-bandwidth memory (HBM), DRAM chips stacked vertically to deliver very fast data access. These parts have to talk to each other across thousands of extremely fine connections, far denser than an ordinary circuit board can carry. The silicon interposer solves this. It is a slab of silicon wired with lithography, the same patterning process used to make chips, so the processor and memory can be packed millimetres apart and connected at chip-level density.

TSMC’s version of this approach is CoWoS, short for chip-on-wafer-on-substrate. Dies are bonded onto an interposer wafer, which is then mounted on a conventional package substrate. In recent years, CoWoS capacity has been widely identified as a binding constraint on AI accelerator shipments. The processors could be fabricated, but there was not enough capacity to package them with their memory. Interposers are one input to that flow. Because they are made in a fab rather than an assembly house, adding interposer supply requires wafer capacity with the right tooling, not just more packaging lines.

What Onshoring One Layer Does, and What It Doesn’t

This is the substance behind the headline. A US-based interposer source moves one fab-made step of AI packaging onto American soil. That has real value. It adds a source outside Taiwan for a component tied to a known chokepoint. It suits a mature, non-leading-edge process, which plays to GlobalFoundries’ strengths in its New York and Vermont fabs. It also gives chip designers and their hyperscale customers, the largest cloud and AI operators, a domestic option to cite when they are asked about supply resilience.

But an interposer alone does not make a finished accelerator. After the interposer is made, the processor dies and memory stacks must be bonded onto it. The assembly must then be mounted on a substrate, tested, and shipped. If those steps remain in Taiwan, US-made interposers simply cross the Pacific in the opposite direction from the processors. Much of the processor output from TSMC’s Arizona fabs has itself needed to return to Taiwan for advanced packaging. The deal becomes a genuinely domestic AI supply chain only when it pairs with US assembly capacity. TSMC said in March 2025 that its expanded Arizona plans include advanced packaging facilities, and its October 6-K shows continued financial support for US subsidiaries, recording lending to TSMC Washington and guarantees for TSMC Arizona. Connecting the interposer supply to that assembly capacity is the step that would turn a single onshored layer into an onshored package.

The packaging variant also matters. TSMC’s family includes the original CoWoS-S, which uses a full silicon interposer, and newer variants such as CoWoS-L, which replace the full interposer with smaller embedded silicon bridges. If flagship accelerators continue shifting toward bridge-based designs, the market for full-size interposers looks different. Which products these US interposers serve will determine how much of the bottleneck they actually touch.

Reading $2 Billion Against Each Company’s Scale

For TSMC, the figure is modest. Its September revenue was about NT$511.86 billion, and its year-to-date revenue was NT$3,898.73 billion, up 41.1 percent. A $2 billion agreement is not a material financial event at that scale. It is a capacity and location decision. Choosing a domestic partner for a mature-process component frees TSMC to focus its own capital elsewhere while adding a US element to its packaging chain.

For GlobalFoundries, the calculus runs the other way. A foundry that chose in 2018 to stop pursuing the most advanced process nodes now has a direct line into the most supply-constrained segment of the AI hardware market, using processes it already runs. That makes it a significant win, though its annual revenue impact cannot be assessed until the contract’s duration and ramp are known. The two companies were once adversaries in a patent dispute that they settled in 2019 with a broad cross-license. A supply relationship on AI packaging is a notable evolution from that history.

Background

TSMC, founded in Taiwan in 1987, is the world’s largest contract chipmaker. It manufactures processors for most leading AI chip designers, and its CoWoS packaging has become central to AI accelerator supply. It is building fabs in Arizona and has said its US plans include advanced packaging. GlobalFoundries, spun out of AMD in 2009, runs fabs in Malta, New York; Essex Junction, Vermont; Dresden; and Singapore. It stopped pursuing the most advanced process nodes in 2018 to focus on specialty technologies.

The two companies settled a patent dispute in 2019 with a broad cross-license. Their new interposer agreement places GlobalFoundries’ US mature-process capacity inside the AI packaging flow that TSMC dominates.

Sources

Source: GlobalFoundries and TSMC reach $2B deal for US-based silicon interposers (Yahoo Finance): report of a $2 billion agreement covering US-made silicon interposers.

Primary sources: Taiwan Semiconductor Manufacturing Company, Form 6-K filed 2026-10-08 (TSMC September 2026 Revenue Report).

TL;DR · 30-second read

The Short Version

The chips behind AI tools like chatbots are not just manufactured. They are also assembled: several chips are placed side by side or stacked, then wired together into one package. How well that assembly works now affects how fast new AI chips can ship.

TSMC, the Taiwanese company that makes many of the world’s AI chips, is building a center in southern Taiwan to test new assembly machines and materials before they reach the factory floor. The goal is to catch problems early, instead of fixing them while production is already running.

Do not expect quick results. The center is due to open in late 2029.

Kaohsiung’s Baipu Industrial Park broke ground on September 21, 2026. SemiVision reported that TSMC will anchor the park with an advanced-packaging training and validation center. The center is not a production line. It is a facility where TSMC and its suppliers will jointly develop, test and qualify packaging equipment and materials. Earlier plans put TSMC’s initial site at roughly three hectares with two buildings, and operations are expected to begin around the fourth quarter of 2029.

The park covers about 88.7 hectares, including roughly 53 hectares of industrial land. Around 25 hectares of that are expected to focus on advanced back-end semiconductor equipment and related supply chains. Official estimates suggest the park could eventually generate around NT$300 billion in annual output and more than 4,000 jobs.

Executive Summary

TSMC’s Baipu center is built around a reconfigurable “Mini-Loop” validation platform. It will not house a complete CoWoS production line. Instead, selected process modules will be assembled, tested and swapped out as technologies change. CoWoS (Chip-on-Wafer-on-Substrate) is TSMC’s technique for placing an AI processor next to stacks of high-bandwidth memory (HBM) inside a single package, and it sits at the core of today’s AI accelerators.

The significance lies in what TSMC is separating out. It is moving equipment and materials validation out of its production fabs and into a dedicated site shared with suppliers. Validation is the work of proving that a new tool or material performs reliably enough for mass production. The move is a bet that AI chip supply increasingly depends on how quickly new packaging tools and materials can be qualified, and not only on how many packaging lines exist.

For suppliers, the promise is earlier entry into TSMC’s development cycle. For AI chip designers, the payoff, if it comes, is fewer surprises when new package designs reach volume production. Neither benefit is expected before late 2029.

Why the Gating Step Is Qualification Time, Not Floor Space

Front-end chipmaking, the step where transistors are patterned onto wafers, relies on equipment giants such as ASML, Applied Materials, Lam Research and Tokyo Electron. These companies run large R&D organizations and global field-service teams that help get new tools qualified. Advanced packaging has no equivalent bench strength. Many back-end equipment suppliers are much smaller, yet a long list of technologies is changing at the same time:

• CoWoS itself
• Hybrid bonding, which fuses chips copper-to-copper without solder bumps
• Thermocompression bonding (TCB)
• Temporary bonding and debonding
• Wafer and panel handling
• Automated optical inspection and metrology
• Underfill, dielectric and thermal materials

The product cadence on top of that is accelerating. NVIDIA, AMD, Broadcom and custom AI chip (ASIC) developers keep introducing new architectures. HBM is moving from HBM3E toward HBM4 and beyond. Package size, die count, interconnect density and heat load are all rising together. The practical result is that one generation of equipment may not finish qualification before the next product generation arrives. Historically, some packaging tools were still being modified after installation, with engineers tuning them while production was already underway. A line that is being debugged is not yielding at full rate.

Baipu is TSMC’s structural answer: move troubleshooting upstream, so that equipment, material and integration problems surface before mass production. This is why capacity counts alone understate the constraint. A packaging plant full of tools that are not yet qualified for the next package design cannot ship the next accelerator. Two groups are most exposed. The first is accelerator designers, whose launch timing depends on new package formats. The second is smaller back-end toolmakers, who have lacked a place to prove their equipment at the pace TSMC’s customers now demand.

The Mini-Loop Is a Capital-Efficiency Choice

A fixed, full-scale experimental packaging line would require heavy capital expenditure. Because 3D IC, CoWoS, HBM and chiplet architectures are evolving quickly, that line’s configuration could be outdated within a few years. The Mini-Loop concept avoids this. TSMC brings in only the module that needs validating, tests it, modifies it, and then reconfigures for the next job. The validation infrastructure evolves with each technology generation instead of being written off along with the previous one.

The trade-off is fidelity. A modular loop tests modules. Some integration problems only appear when every step runs together at volume, and those may still surface in production. How much time Baipu actually saves will depend on two things: how TSMC bridges that gap, and whether validation results at Baipu carry directly into production qualification or must be partly repeated in the fabs.

From Equipment Vendor to Co-Development Partner

The conventional sequence runs like this: the customer sets a specification, the supplier builds the tool, the tool is installed in the fab, qualification begins, and then the equipment is modified in response to feedback. Baipu aims to put customers, equipment makers, materials companies and research organizations into the same development loop before mass production begins. In that loop, equipment fixes can happen immediately, and materials can move straight into another design of experiments (DOE, a structured test matrix). Software, automation, process recipes and metrology can all be tuned in parallel.

This is a different advantage from simple proximity. Being near TSMC saves shipping and service time. Entering its development cycle early lets a supplier help shape the specification instead of chasing it. The groundbreaking drew companies from across the stack: TSMC, ASE, Foxconn, ASPEED, WinWay, King Slide, Gudeng, C SUN, Grand Process Technology, Scientech, AblePrint, HIWIN and Gallant Precision Machining. Attendance does not confirm investment. The first phase is expected to include validation work linked to TSMC and its suppliers, along with Foxconn AI-related R&D and manufacturing. A later phase could support further advanced-packaging expansion, including requirements from companies such as ASE.

Kaohsiung presents Baipu as one link in a southern-Taiwan corridor:

• Nanzih: advanced semiconductor manufacturing
• Renwu: packaging and test
• Ciaotou: materials and critical components
• Gangshan and Lujhu: existing precision-machinery, metal-processing and fastener industries that the city hopes to pull into the equipment supply chain

If that works, the regional advantage would not rest on any single fab. It would rest on how tightly manufacturing, packaging, equipment and qualification can iterate over short physical distances.

What a 2029 Opening Means for Today’s AI Supply

With operations expected around the fourth quarter of 2029, Baipu sits outside the window of current packaging constraints. Tools and materials qualified there would serve product generations well beyond today’s HBM3E-based parts. Buyers of AI accelerators should not read Baipu as near-term relief. It is an investment in the rate at which packaging technology can change over the following years.

The headline economic figures are NT$300 billion in annual output and more than 4,000 jobs. These are park-wide official estimates, not TSMC commitments, and they say little about the metric that matters most to the industry: how much shorter qualification cycles actually become. No such target has been published. The argument that time-to-qualification is becoming the gating factor is coherent and fits the direction of packaging technology. Its payoff, however, will only be measurable in how many Baipu-validated tools reach production lines at TSMC, ASE or other manufacturers.

Background

TSMC (Taiwan Semiconductor Manufacturing Company) manufactures chips designed by other companies. In the AI era, its role has extended from wafer fabrication into advanced packaging. Packaging is the step where multiple chips, such as a processor and stacks of high-bandwidth memory, are combined into a single package. Technologies such as CoWoS, hybrid bonding and 3D IC stacking have made packaging a performance-critical part of AI accelerators, and HBM, substrates, thermal management, metrology and automation have become increasingly interdependent.

Southern Taiwan is a focal point of that build-out. Kaohsiung’s semiconductor base already spans Nanzih, Renwu and Ciaotou. The city is positioning Baipu Industrial Park, which broke ground in September 2026, as both an advanced semiconductor equipment and materials validation hub and an AI advanced-manufacturing base.

Sources

Source: Beyond Capacity Expansion: TSMC Builds an Advanced Packaging Validation Hub in Kaohsiung (SemiVision), an analysis of TSMC’s planned advanced-packaging validation center at Kaohsiung’s Baipu Industrial Park.

TL;DR · 30-second read

The Short Version

The chips that run artificial intelligence are not held up by the factories that print them. They are held up by the assembly step at the end, where a processor and its memory are bonded onto a single slab so they can talk to each other fast enough.

Taiwan Semiconductor Manufacturing Company owns most of the world’s capacity for that step. Analysts in Taiwan say it plans to roughly double that capacity by 2028. Until it does, anyone building an artificial intelligence data center is standing in a queue. Intel is selling a rival method, and smaller assembly firms are absorbing the overflow.

Wccftech, citing a Taiwanese media report that quotes analysts, said TSMC plans to expand its chip-on-wafer-on-substrate (CoWoS) advanced packaging capacity to 260,000 wafers per month by the end of 2028, roughly double the approximately 130,000 wafers per month the same forecast puts it at by the end of 2026. The expansion is said to center on TSMC’s Arizona campus and its AP7 packaging facility in Taiwan.

The same forecast estimates that Intel’s competing EMIB-T packaging, converted into CoWoS-equivalent 12-inch wafer terms, could reach 15,000 to 20,000 wafers per month in 2027 and 40,000 to 45,000 in 2028, and says the CoWoS shortage has pushed work toward other packaging firms including Amkor, UMC and ASE. TSMC has not published a capacity target of its own. In a Form 6-K filed with the Securities and Exchange Commission on September 10, the company reported August 2026 consolidated revenue of NT$514.81 billion, up 53.3 percent from a year earlier.

Executive Summary

Advanced packaging is the step where a logic die and its stacks of high-bandwidth memory are mounted together onto a shared substrate so they behave as one component. CoWoS is TSMC’s version, and it is the packaging used for the accelerators that fill AI data centers. For roughly three years it, rather than leading-edge wafer manufacturing, has been the narrowest point in the supply chain for those parts.

A doubling of that capacity by 2028 would be the single largest change to AI hardware availability that any one company can make. It would not, however, double accelerator output in a straight line. Package sizes are growing, the newest designs consume more interposer area and more memory stacks per unit, and a wafer of packaging substrate therefore yields fewer finished accelerators each generation than it did the year before. Capacity that doubles against demand that also rises per unit is not the same as supply that doubles.

TSMC’s own disclosure does not address packaging capacity. What its September 10 filing does show is demand running hot: August revenue rose 53.3 percent year over year, and revenue for the first eight months of 2026 was up 39.3 percent. That is consistent with a company selling everything it can finish, which is the condition under which a capacity forecast of this kind becomes credible without being confirmed.

The Bottleneck Moved Downstream

For most of the history of the chip industry, the scarce resource was the front end: photolithography tools, leading-edge wafer starts, yield on a new process node. Packaging was the cheap, unglamorous back end. AI accelerators inverted that. A modern accelerator is not one chip but an assembly, a large logic die surrounded by stacks of memory, all sitting on a silicon interposer threaded with vertical connections called through-silicon vias. The density of those connections is what delivers the memory bandwidth the workload needs. That assembly step is CoWoS, and there is no abundant substitute for it.

The practical consequence for anyone financing a data center is that wafer capacity is no longer the number to watch. A foundry can start more wafers than it can finish into packages, and unfinished silicon does not train models. The forecast of 130,000 wafers per month at the end of 2026 rising to 260,000 by the end of 2028 is, in effect, a two-year schedule for how quickly the industry can convert build-ready halls into loaded racks.

Read it with care, though. Interposer area per accelerator has been climbing with every generation as designers add memory stacks and reticle-stitched logic. If the average package consumes meaningfully more of a wafer in 2028 than it does today, unit output grows by considerably less than the wafer count suggests. Doubling the input is a ceiling on supply growth, not a promise of it.

Arizona Can Print the Chips but Cannot Finish Them

The most operationally interesting detail in the forecast is geographic. Wafers produced at TSMC’s Arizona campus are flown to Taiwan to be packaged, because the packaging capacity sits on the island. Siting part of the expansion in Arizona alongside the AP7 facility in Taiwan would begin to close that loop, turning an American fab from a wafer source into something closer to a finished-component source.

That matters for reasons beyond logistics. A round trip across the Pacific adds days of cycle time and a customs and freight cost to every high-value wafer, and it means that the resilience argument for building fabs outside Taiwan is currently incomplete. A domestic fab whose output must still transit Taiwan to become a usable product does not remove the concentration risk that justified it. TSMC’s own filing shows the Arizona entity is treated as a significant subsidiary, with parent guarantees extended to TSMC Arizona among other affiliates, but the filing says nothing about packaging there.

For data center operators and the governments underwriting them, this is the question worth asking of any onshoring announcement: does the site produce a wafer or a shippable part? Until packaging follows fabrication, the answer for Arizona remains the former.

Intel’s EMIB-T and the Value of a Second Source

Intel’s EMIB-T takes a different architectural route. Instead of building the whole assembly on a large silicon interposer, it embeds small silicon bridges inside the organic substrate and places the logic and memory dies on top. Less silicon is used, which can mean lower cost and fewer of the handling and warpage problems that come with very large interposers, but the approach historically trades away some of the interconnect density that the largest, most bandwidth-hungry designs demand.

The forecast puts EMIB-T at 40,000 to 45,000 CoWoS-equivalent wafers per month by 2028. Against 260,000, that is a meaningful second source rather than a competitive threat, on the order of a sixth of the leader’s volume. The claim that it suits custom accelerators of the kind Google and Amazon design is plausible on architecture, since in-house cloud silicon is generally tuned for a known workload and a known cost target rather than for maximum bandwidth per package. It is also unverified: neither Intel nor any cloud provider has announced such an arrangement.

The spillover to Amkor, UMC and ASE follows the same logic. When the preferred supplier is sold out, work migrates to whoever can perform an adjacent version of it, and outsourced assembly and test firms have been the natural landing place. Buyers get optionality and a check on pricing. The risk is that second-source packaging is not a drop-in substitute. Requalifying a part on a different packaging architecture is an engineering program, not a purchase order, and the customers best placed to do it are the ones designing their own silicon.

What Is Substantiated and What Is Not

The demand side of this story rests on disclosed figures. TSMC’s September 10 filing with the Securities and Exchange Commission reports August consolidated revenue of NT$514.81 billion, a 10.1 percent increase on July and 53.3 percent on August 2025, with the first eight months of 2026 up 39.3 percent year over year. Growth at that rate at TSMC’s scale is difficult to explain without sustained AI accelerator demand behind it.

The supply side is a forecast, not a commitment. The 260,000 figure, the 130,000 baseline, the Arizona and AP7 split and the EMIB-T range all come from analysts rather than from the companies. None of the three firms named has published a packaging capacity target, a capital budget attached to one, or a schedule. Analyst capacity models in this industry have a reasonable track record on direction and a poorer one on timing, because packaging expansions depend on tool delivery, cleanroom construction and qualification cycles that slip quietly.

The sober reading is that the direction is well supported and the magnitude is an estimate. Treat 2028 as the earliest plausible date for materially looser accelerator supply, treat the doubling as a ceiling rather than a plan of record, and treat any procurement model that assumes it as carrying schedule risk that TSMC has not underwritten.

Background

TSMC is the world’s largest contract chip manufacturer, building processors designed by other companies. It commercialised CoWoS in the 2010s as a niche technique for high-performance parts, long before AI accelerators turned it into the scarcest resource in the industry. Today the packaging step determines how many finished accelerators reach the market, because a logic die without its memory bonded alongside it is not a usable product.

The competitive response has come from two directions. Intel has pushed its own bridge-based packaging as part of its foundry ambitions, targeting customers who want a supplier outside Taiwan or a lower-cost assembly for custom silicon. Outsourced assembly and test firms such as Amkor, ASE and UMC have absorbed work that TSMC cannot schedule. None of this has yet changed the basic shape of the market, in which one company’s packaging line sets the pace at which AI data centers can be filled.

Sources

Source: Report: TSMC to Double CoWoS Capacity by 2028 as AI Chip Shortage Spills Over to Rivals, which relays a Taiwanese analyst forecast for TSMC’s advanced packaging capacity and for Intel’s competing EMIB-T volumes.

Primary sources: Taiwan Semiconductor Manufacturing Company, Form 6-K filed September 10, 2026 (August 2026 revenue report), filed with the US Securities and Exchange Commission.