TL;DR · 30-second read

The Short Version

Nvidia, whose chips power much of today’s artificial intelligence, is designing its own version of the ultra-fast memory that sits right next to those chips.

Samsung, normally a rival of Taiwan Semiconductor Manufacturing Company, has reportedly agreed to let the Taiwanese firm build the memory’s bottom layer, the part that talks to the chip. Nvidia’s two other memory suppliers are on the same plan.

Three memory makers, one factory process underneath. That makes testing quicker. But if that one supplier runs short, all three wait together, and so do the companies building artificial intelligence data centers.

Wccftech reported on November 7, 2026, citing Seoul Economic Daily, that Samsung and TSMC are jointly developing the base die for Nvidia’s custom high-bandwidth memory, known as NVHBM, on TSMC’s 3nm manufacturing process. Nvidia has asked Samsung, SK hynix and Micron to build NVHBM base dies on that same TSMC node, and to make the DRAM layers stacked above them on the sixth-generation “1c” DRAM process. Samsung has accepted, its first departure from the “turnkey” model in which it makes both layers itself.

Nvidia has said the custom memory, planned for its Feynman-generation GPUs, can deliver up to 30 percent more bandwidth than standard HBM4E at up to 15 percent lower power. Separately, TSMC denied any plan to mass-produce 3D DRAM, indicating it will remain focused on logic chips.

Executive Summary

The news concerns the least visible part of the memory packaged beside an AI accelerator. High-bandwidth memory (HBM) is a tower of DRAM chips sitting on a base die, a logic chip at the bottom that manages the connection to the GPU. Under the arrangement described, Nvidia standardizes that base die on a single TSMC process across all three memory makers it buys from, so it can validate one design rather than verifying each vendor’s samples separately.

That matters for AI infrastructure because memory supply helps determine when accelerators ship. A common base die promises consistent performance and faster qualification, but it also means Nvidia’s three-supplier memory strategy now rests on one foundry node. Samsung is still evaluating its own foundry as a backstop in case NVHBM demand exceeds TSMC’s production capacity, which signals that capacity at that node is the variable to watch.

Three Memory Suppliers, One Foundry Dependency

Buying memory from several manufacturers has traditionally worked as a hedge: if one supplier’s yields slip or a factory is disrupted, the others can absorb the volume. The NVHBM plan keeps three suppliers at the memory layer, with Samsung, SK hynix and Micron each building DRAM core dies on the 1c process, but routes every base die through TSMC’s 3nm node. Diversification now stops one layer short of the bottom of the stack.

The mechanism is simple. A finished HBM stack cannot ship without its base die, so the number of NVHBM stacks any of the three memory makers can deliver is capped by the 3nm wafers TSMC allocates to the program. A shortfall or delay at that node would not hit one supplier; it would hit all three at once. Samsung’s decision to keep its own foundry under evaluation in case demand outruns TSMC’s capacity shows that the participants already treat 3nm availability as the constraint to plan around.

The effects run downstream as well as upstream. Nvidia carries the concentration risk directly. Memory makers become dependent, for this product, on a foundry allocation they do not control. And cloud providers and data center operators planning Feynman-era deployments inherit a supply chain in which the timing of memory, and therefore of the accelerators that need it, depends partly on a logic foundry’s capacity decisions rather than on DRAM output alone.

Why Nvidia Would Accept the Concentration

The trade-off has a clear rationale. Nvidia’s stated targets of up to 30 percent more bandwidth than HBM4E and up to 15 percent lower power depend on every stack behaving the same way. If each memory maker built its base die on its own process, Nvidia would have to verify each vendor’s samples separately. A common 3nm base die and a common 1c core process mean one design to validate, saving engineering time on every product cycle.

The performance figures deserve careful reading. Both are “up to” numbers, both are Nvidia’s own promises rather than measurements from shipping parts, and Nvidia has not specified which HBM4E configuration serves as the baseline. They describe a design goal, not demonstrated performance.

Power is where the claim reaches data center operators most directly. Memory power adds to the heat load of every accelerator package, so a 15 percent reduction, if delivered, would ease rack power and cooling budgets somewhat. How much depends on memory’s share of total package power, which has not been disclosed.

Samsung’s Foundry Math Gets More Complicated

For Samsung, the arrangement is a notable concession. It is the first time the company has stepped away from its turnkey model of designing and manufacturing both the core and base dies in-house. Its standard HBM will remain turnkey; only NVHBM moves the base die to TSMC.

The decision sits awkwardly against Samsung’s foundry economics. HBM has been credited with helping narrow the foundry division’s losses, which an earlier estimate put at 6.74 trillion won (about $5.1 billion) in 2025, falling 41 percent to 3.92 trillion won (about $2.95 billion) in 2026. Ceding the NVHBM base die to a direct foundry competitor forgoes logic wafer volume Samsung’s own foundry could have used, which helps explain why Samsung is keeping that foundry in reserve as an overflow option.

Whether the overflow path is practical is a separate question. A base die made at a second foundry would, by definition, be a second process for Nvidia to validate, the very burden standardization is meant to remove.

TSMC Gains a Memory Role Without Making Memory

TSMC’s position is the mirror image. It enters the HBM supply chain as the source of a component every NVHBM stack needs, while declining to enter DRAM manufacturing: it has denied any plan to mass-produce 3D DRAM and is staying with logic chips. That keeps TSMC out of the memory business and its pricing cycles while making it indispensable to this product.

For the industry, the arrangement shows how AI memory in this design has become a hybrid of memory and logic manufacturing. The DRAM layers still come from memory makers; the interface layer that shapes performance comes from a logic foundry. Capacity planning for this generation of accelerators has to account for both.

Background

High-bandwidth memory is stacked DRAM placed in the same package as an AI accelerator, where it feeds data to the processor far faster than conventional memory modules. Three companies make it: Samsung, SK hynix and Micron. Each stack consists of DRAM core dies on top of a base die that handles communication with the processor, and each new generation, most recently HBM4 and HBM4E, raises bandwidth. Samsung has historically built both layers itself, an approach it calls turnkey.

TSMC is the world’s largest contract chipmaker and manufactures Nvidia’s GPUs. Samsung both makes memory and runs a foundry business that competes with TSMC for logic customers, which is why a joint base-die effort between the two stands out. Nvidia’s Feynman architecture follows its current GPU generations and is slated to use NVHBM.

Sources

Source: NVIDIA’s Development Of Custom HBM Drops Samsung’s And TSMC’s Foundry Rivalry, As Both Manufacturers Join Forces To Develop “Base Die” On The 3nm Node [Update] (Wccftech) — Samsung and TSMC jointly develop a 3nm base die for Nvidia’s custom NVHBM, with SK hynix and Micron asked to use the same node.